The dynamic range of conventional analog low-voltage circuits is greatly limited. In order to achieve an optimum output for a predetermined power input, a voltage range which can be processed by analog circuit parts is maximized. In the case of a low-voltage CMOS circuit, the output stages of operational amplifiers are thus located close to a supply voltage (rail-to-rail), i.e., only a transistor is disposed between the output of the operational amplifier and the supply voltage.
A typical fully differential two-stage operational amplifier circuit is represented in FIG. 1. In the amplifier circuit of FIG. 1, the Miller effect is compensated, the output stage is located close to the supply voltage, and feedback is provided for feedback control of the mid-voltage. An operational amplifier 12 amplifies a difference between an externally settable voltage VCM and a mean value of the voltage value of two outputs 3, 4 of the operational amplifier circuit such that the mean value is set to the voltage VCM. In order to maximize the available voltage range at the output of the fully differential operational amplifier circuit, the voltage VCM should be set exactly in the middle of a voltage range in which the two output transistors N2 are in saturation. That is to say, the optimum voltage VCMopt must satisfy the following equation:
                              VCM          opt                =                              1            2                    *                      (                                          V                DD                            -                              V                SS                            -                              V                                  DSAT                  ,                  P2                                            -                              V                                  DSAT                  ,                  N2                                                      )                                              (        1        )            
In equation (1), VDD, VSS are supply voltages and VDSAT,P2, VDSAT,N2 are saturation voltages of the output transistors N2. FIG. 2 shows an abstract model of the fully differential operational amplifier circuit of FIG. 1. The voltages at the outputs 3, 4 of the fully differential operational amplifier 11, which also correspond to the outputs 3, 4 of the fully differential operational amplifier circuit, are averaged by an averaging network 13, and a difference between a voltage present at a circuit node 5 and the externally settable voltage VCM is amplified and supplied to the control input 7 of the fully differential operational amplifier 11. In this case, the voltage VCM can also be applied as standard to the two gate terminals of two input transistors P1 of the fully differential operational amplifier 11. In this case, however, certain problems occur.
In the case of very small supply voltages, the input transistors P1 use a bias voltage that is less than VCMopt. If, however, the voltage VCM is reduced from the optimum voltage VCMopt, the voltage range of the output 3, 4 of the fully differential operational amplifier circuit is reduced by double the amount of reduction. In addition, other circuit parts may have an optimum mid-voltage which differs both from the voltage VCMopt and from the optimum bias voltage of the input transistors P1.
The problems described above may be solved by making available different voltages and buffering these voltages in an appropriate manner. However, this solution increases the complexity and power consumption of the circuit.